The Visualization Series was developed to provide input and output capability for a real-time video supercomputer developed at a leading television research laboratory. The original hardware was delivered in 1988. Continual improvement of the system has led to the second and third generation hardware described here. These products are available to customers outside the supercomputing industry. System engineering and design of additional modules is available.
The system occupies a 19" rack mounting 6U card file with attached power supply. Input and output to customer equipment is through TTL ribbon cables. Wire--wrapped wiring of the card file backplane allows the system to be configured to customer requirements.
Digitizes an analog input signal with a precision eight-bit ADC. Selectable input filters and clamping modes allow easy switching to accomodate input signals. An internal 9K pixel FIFO memory allows digitized signals to be reformatted to differing output standards.
Accepts a D1, D2 or SMPTE 260M1 parallel digital data stream on a standard DB-25 Connector. Sync detectors accept D1 or D2 style sync. Internal FIFO operates similar to ADC2 unit to allow standards conversion and asynchronous modes.
Digital Genlock acts as the clock
source for all modules. It allows sampling of user-defined input
signals at sample rates of 10 to 80 MHz. Burst lock to NTSC, PAL,
and "Sony Burst 1125/60" signals is possible at
arbitrary rates. Recursive/Adaptive digital signal processing
allows robust sampling of 0dB SNR signals.
Asynchronous Handshaking between two GL-1's allows standards conversion, raster/ format remapping. Sampling of two asynchronous inputs with common synchronous output possible with two GL-1's.
Supports raster sizes up to 2K x 2K 32-bit pixels at 80 MHz sampling rates. Versitile address generator allows windowing and scrolling of data. Full double buffering and close coupling to GL1 cards allow use in standards conversion/reformatting modes.
Reconstructs a digital input signal with a precision ten-bit 160MHz DAC. Internal 2K pixel FIFO allows input signals to be resynchronized to asynchronous output clocks provided by a secondary GL1. Programmable blanker generates cosinusoidially-shaped blanking edges and levels on input signal. Eight-line waveform storage allows optional insertion of sync or test signals. Signal generation software allows user generation of standard video test signals and sync waveforms at selected sample rate
Provides a balanced ECL parallel digital video output on a standard DB-25 connector. The pixel clock and data multiplexing may be adjusted to provide signals in D1, D2, and SMPTE 260M1 formats. FIFO, blanking and waveform insertion capabilities are identical to the DAC2 Unit.
Specifications subject to change without notice. Product names may be trademarks of their respective manufacturers. Image Circuits is a registered trademark of Image Circuits, Inc. Copyright 1997 Image Circuits, Inc. ALL RIGHTS RESERVED.
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