TCD Series Monitoring Transcoders Product Data
TXA Series Digitizing Transcoders Brochure
Series Monitoring Transcoders
or D1 parallel digital video to RGB or YPrPb analog
output. DB-15 connector for directly driving multi-sync
computer monitors for economical HDTV monitoring.
Accepts SMPTE 260M or Sony HDD-1000 digital video on 50-pin input connector. Regenerated loop-through output allows insertion in existing signal path.
Active loop-through parallel input regenerates output signal
Economical output filters provide group delay and sin(x)/x equalized output suitable for monitoring.
Optional high-performance output filters provide full SMPTE 260M compliance with ±0.05dB, 1nS ripple.
video DACs and precision analog circuits.
Internal analog transcoder provides RGB output with SMPTE 240M matrix.
1V BNC SMPTE 240M outputs with tri-level sync. D1 units provide bipolar sync.
Analog video outputs with TTL sync on VGA high-density DB-15 connector for Multi-sync monitor.
1 MOhm probe input with adjustable gain, offset, and polarity allows overlay of signal or cursor on output for laboratory work. Input has switchable 75 Ohm termination for video signal overlay.
Pulse-Cross display mode internally selectable for technical monitoring.
|TCD-1125||1125/60, 1125/59.94 Sony HDD-1000 Format|
|TCD-525||SMPTE 125M/CCIR 601,656 D1Format, 525 line (NTSC)|
|TCD-625||CCIR601,656 D1 Format, 625 lines (PAL)|
|Option 01||SMPTE 240M, CCIR 601 compliant high quality filters|
|Option 02||Switchable serial loop-through input (525,625 models only)|
|Option 03||YPrPb Output|
|Option Y||220VAC Power Input|
HDTV Image Capture
series units digitize normal and high-definition analog
component video signals at user-programmed sampling rates
into a TTL or D1-style digital output. Oversampling ADCs
and digital anti-alias filtering maximize signal quality.
Internal digital transcoders and decimation filters allow
conversion between YPbPr and GBR signal formats. A
versatile programmable genlock circuit allows
resolution-independent capture of input signals with both
sync and burst locking. Digitizing of NTSC or PAL signals
into D2 formats is also possible.
HDTV Image Sampling Approches the Ideal
With the TXA series, Image Circuits introduces its fourth generation of HDTV digitizers. Advances in ADC technology allow the use of over-sampled digitizing, resulting in ideal system frequency and phase response. Filtering, transcoding, decimation, and clipping of component signals is performed digitally for increased stability and precision.
Programmable Sampling for Future Standards
To allow continued use as HD production standards evolve, the TXA series is fully programmable. All signal path parameters, such as clamp level, input voltage, decimation filters, transcoding coefficients, blanking envelope, and amplitude clipping are programmable by the user through the TXA operating software. Genlock parameters may be similarly adjusted to set values for pixels per scan line, lines per field, fields per frame and active picture region. Standard video test signals may be generated from the users sampling parameters and inserted over the digitized input.
Hybrid Genlock with Tri-level Sync, Bipolar Sync, and Burst Locking
The genlock circuit allows locking to bipolar and tri-level sync or to the color burst of NTSC and PAL signals. Subcarrier signals for burst locking are digitally synthesized, allowing locking at non-integral multiples of the burst frequency and precise adjustment of sampling phase. The genlocks hybrid analog/digital design incorporates precision analog phase comparators which allow sampling with sub-nanosecond sampling jitter. Two auxiliary crystal oscillators may be selected for sampling with extremely low jitter at specified frequencies.
Oversampling Input with 0.05dB, 2nS Ripple Filtering
Three identical input channels allow individual software control of clamping level, full-scale range, and input filtering. This allows the TXA series to accommodate both RGB and color-difference signals. Image Circuits digital clamp technology insures a stable, drift-free clamp level with any input signal.
Each channel contains four analog pre-filters which are selected to match the input sample rate. As the channels ADC operates at twice the desired sample rate, these simple pre-filters need only remove alias components above three times the sampling frequency. Digital filtering and decimation following the ADC allow full compliance with the rigorous SMPTE 260 and CCIR 601 filter templates. This method allows the user to sample at arbitrary frequencies without purchasing costly input filters for each frequency.
Digital Transcoding and Decimation Filtering
A 3 x 3 matrix multiplier following the input stage allows transcoding between user-programmed input and output signal formats. Selectable digital filters following the transcoder allow decimation of color-difference signals according to SMPTE and CCIR templates.
A blanking processor following the transcoding section allows the input signals blanking interval to be replaced with appropriate sync words or waveforms. As the blanker is completely programmable, the active picture area can be adjusted by the user or replaced with a test pattern. A programmable look-up table circuit clips the input signal to legal values and optionally provides smooth, cosinusoidally-shaped blanking edges.
Outputs for Lab or Studio
The output signal is available as a standard SMPTE 260 multiplexed ECL signal or as a demultiplexed TTL signal at half the sample rate. Programmable sync and drive signals, as well as a sample clock output, allow easy connection to following equipment. Direct connection to HDTV framestores, such as the Viewgraphics VS-5000, is possible using the TTL outputs.
|TXA-1008, TXA-1018||10-80 MHz|
|TXA-1010||10-40 MHz (40-80 MHz using external filter)|
|Frequency Response||Complies with CCIR 601, SMPTE 260M filter templates at appropriate sample rates|
|90 IRE 0.1 - 30 MHz sweep||1.2% (p-p ripple of p-p amplitude, 75 MHz sampling)|
|Line Tilt (NTC-7 3.4)||0.25 IRE (13.5 MHz sampling)|
|Field Tilt (NTC-7 3.3)||0.25 IRE (13.5 MHz sampling)|
|Multipulse Baseline Ripple||0.3 IRE (13.5 MHz sampling, 100 IRE Tek NTSC signal)|
|Multipulse Baseline Ripple||0.5 IRE (75 MHz sampling, 100 IRE 5,10,15,20,25 MHz Tek signal)|
|2T Pulse Height (NTC-7 3.5)||0.5 IRE (13.5 MHz sampling)|
|2T Pulse Ringing (NTC-7 3.5)||1.0 IRE (13.5 MHz sampling)|
|2T30 Pulse Height||0.5 IRE (75 MHz sampling, 33.3 nS HAD, 100 IRE signal)|
|2T30 Pulse Ringing||1.0 IRE (75 MHz sampling, 33.3 nS HAD, 100 IRE signal)|
|Non-Linearity and Noise|
|Differential Gain, 3.58 MHz||1%|
|Differential Phase, 3.58 MHz||0.5°|
|Luma Noise (IEEE 746)||57dB (75 MHz Sampling, peak signal to rms noise)|
|Input Impedance||75 ohm, Return Loss >35 dB DC to 40 MHz|
Green/Y, Blue/B-Y video signals, 75 ohm BNC
External Sync/Blackburst, 75 ohm BNC
External Clock/Subcarrier 50 ohm BNC, AC coupled with 0.1uF capacitor to 50 ohm termination
|ECL video output||Differential 10K ECL compliant with SMPTE 260M on 93 pin SMPTE connector|
|TTL video output||TTL single-ended output on two SCSI-2 style 50-pin connectors at one-half sampling frequency. 120 ohm source impedance|
|Output Formats||ECL output:
4:2:2 YCrCb SMPTE 260M, D1
TTL output: 4:2:2 YCrCb, 4:4:4 RGB demultiplexed into Y0, Cr, Y1, Cb channels or R0, R1, G0, G1, B0, B1 channels. D2 format TBD
|User Outputs||2 outputs translated to -4V level and filtered to 100nS risetimes on 75 ohm BNC. All outputs available on pins of TTL output connector|
|Sample Clock||10KH ECL output with 50W series resistor to 50 ohm BNC. Internal jumper selects ADC sampling frequency or pixel clock|
|Gain and Clamping|
|Input Full Scale Amplitude||0.7 to 1.4V p-p|
|Input Clamp Level||Any point within ADC full scale range|
|NTC-7 Bounce||<0.25 IRE (13.5 MHz sampling)|
|Blanking and Clipping|
|Blanking Risetime||Y channel:
0-16 samples of F801 clock
C channel: 0-8 samples of F401 clock
|Clipping Level||Minimum and Maximum clip limits may be any 8-bit value|
|Sync Insertion||D2, D1, SMPTE 260 waveforms pre-programmed for optional insertion. User waveforms may be programmed through remote control interface. Waveforms automatically scaled for sampling frequency used.|
|Test Signal Insertion||Color bars, Multiburst, Multipulse, Ramp, Staircase, Pulse and Bar, Sweep, NTC7 Composite|
|Transcoding Coefficients||10-bit integers, 9 fractional bits, two-complement format. Stored values for RGB->YUV transformation in NTSC, CCIR 476, and SMPTE 240M color spaces may be used or custom values downloaded over remote control interface.|
|Chroma Decimation Filtering||2:1 fixed-coefficient lowpass filter compliant with CCIR 601, SMPTE 260M filter templates|
|Genlock Parameters||All position values in F401 clocks relative to input analog sync edge reference point|
|Sampling Frequency||Nearest integer value in Hz (used for scaling sync and test signals only)|
|Clocks per line||32 to 8192, in F401 clock increments|
|Lines per field||32 to 8192, in 1 line increments|
|Fields per frame||1 to 2|
|Lock Mode||Sync Lock,
Sync Lock, tri-level sync
Burst Lock; NTSC, PAL, Sony Burst (1125/60) signals or external subcarrier
|Reference Burst Frequency||1 to 10 MHz in F401·2-32 steps|
|Sample clock phase relative to reference subcarrier||0 to 180° in 360°·2-32 increments|
|Subcarrier phase reset/lock to line 1 sync edge||1 to 255 frames or free-running|
|Clamp Position||Width, position adjustable in F401 clock increments|
|Burst Position||Width, position adjustable in F401 clock increments|
|Burst Vertical Blanking||Width, position adjustable in one line increments|
|Active Raster Width||Width, position adjustable in F401 clock increments|
|Active Raster Height||Height, position adjustable in one line increments|
|Blanker Risetime||Nearest integer in nS (User warned when specified value exceeds maximum samples available)|
|Blanking Level||Level may be any 8-bit value|
|Clipping Limits||Minimum and Maximum clip limits may be any 8-bit value|
|Sync Position||Width, position adjustable in F401 clock increments|
|User Outputs||8 TTL outputs at F401 clock rate programmable as either single pulses with specified width and position or arbitrary pattern by downloading bit pattern through remote control interface.|
|Minimum SNR of stable input for PLL acquisition||15 dB, peak-to-peak signal to RMS noise|
|Minimum SNR of stable input for PLL lock||10 dB, peak-to-peak signal to RMS noise|
|Sampling Jitter, VCXO||±200 pS, 50dB SNR input signal|
|Sampling Jitter, VCO||±500 pS, 50dB SNR input signal|
|Remote Control||RS-232 or RS-422, 9600 or 38,400 baud serial link to terminal or computer supporting VT-100 command set.|
|Power||IEC 320/VI power receptacle, 85-132VAC, 47-63Hz 150W maximum|
|Physical and Environmental|
|Operating Environment||10-35°C, 10-90% relative humidity, normal office or laboratory environment|
RS-310 19"x2U enclosure, 20" depth,
1F40 is the VCO or VCXO frequency (80-160 MHz) divided by 4.
Specifications subject to change without notice. Product names may be trademarks of their respective manufacturers. Image Circuits is a registered trademark of Image Circuits, Inc. Copyright 1997 Image Circuits, Inc. ALL RIGHTS RESERVED.
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